SB375 Clock Table Revised

A number of minor errors in the SB375 clocking table have been corrected.  Reference pixels are now properly registered in the first four columns and the last four, and our effective active area is now 1024 rows x 1016 coulmns after discarding the outermost eight columns of active pixels in order to fit the reference pixels ino the 1024x1024 array format required by the existing software.

Because the SB375 busses four reference columns onto a single unit cell amplifier, the new clocktable allows four times more settling time on the reference pixels.  The code appears to work fine, and much of the fine scale horizontal striping has gone away with this fix.  The new clock table (v.1) will be uploaded to PBMA, and is reprinted below for reference:

**************************
# Clocking table generation file for SB375/EXES v.1
#
# This file generates a clocking bit table for use in the EXES instrument.
#
#
# Revision History:
#
# 10.11.18 - Revised to a sample reference pixels instead of outside cols of
#            active pixels, and to fix registration problems.  MMcK
# 10.09.08 - Initial.  MMcK, based on SB226_v2_1.btg
#
# Notes:
# SB375 has no dedicated sync pulses for the row and col muxes.  The sync function is
# accomplished by simultaneous assertion of the two shift register clocks.
#
# Clock labels:
# pR1 = slow (row) phase 1 (-2/-5)
# pR2 = slow (row) phase 2 (-2/-5)
# pC1 = fast (col) phase 1 (-2/-5)
# pC2 = fast (col) phase 2 (-2/-5)
# prston = reset pulse (-2/-5)
# prowon = opposite of prston
#
# Restrictions:
#-prstminimum time tbd (25us?).
#
#-'underlap' or shift register phases must be maintained to avoid unintentional sync
#
#-row and column muxes require a 'preamble' to initialize them.
#
#-preamble consists of asserting both phases to reset, then a period with both phases
# de-asserted, then a period with phase 1 asserted, then a period with both phases
# de-asserted.  First valid row/col address is obtained on next assertion of phase 2.
# Nominal pattern for the preamble is H 5 5 4 for phase 1, H 5 10 for phase 2.  First
# (reference) column is addressed with assertion of phase 2 on timeperiod 16.
# Col mux preamble occurs once per row, row mux preamble occurs once per scan.
#
#-SB375 array format is 1024 rows by 1032 columns, with 1024 columns of active pixels
# flanked by 4 reference columns on each side.  There are no reference rows.
# Reference columns differ from active pixel columns in that a) they have no detector
# attached so capacitance is slightly different and b) a sigle unit cell feeds all
# four reference columns on an edge so the drive current available and time constant
# differ by x4.  We provide 4x more settling time for the reference columns to
# account for this.
#
#-Because our present FPGA software can only deal with 1024x1024 array format,
# can't sample all 1024x1032 elements of the SB375.  The reference pixels are
# presently deemed more valuable, so the clock table digitizes the reference columns
# in place of the first and last columns of active pixels.
#
#-The SB375 resets rows in pairs, with the reset function enabled on the even
# (second) row of each pair.  Odd rows can be reset only after stepping on to the
# subsequent even row.  The row mux will not run in reverse, so it is not possible
# to run a 'delta-reset' sampling scheme as is done in TEXES.
#
#-The clock table is written around a basic building block of 10 time periods per
# unit cell pair. Each unit cell is held valid for 4 time periods, and the
# required underlap adds 2 time periods of overhead per pair.
#
#-The four outputs are sampled simultaneously, so digitization of the 1016 columns
# of active pixels requires 10 * 1016/8 = 1270 time periods. To this time we add 34
# additional time periods to sample the pair of reference columns (16 time periods
# asserted for each ref column, plus two time periods for underlap), plus 10 time
# periods to clock through (but not digitize) the two columns of discarded active
# pixels plus 15 time periods for the preamble and 25 time periods for the reset
# pulse.  In this edition of the clock table we clock all the rows symmetrically,
# whether they are even or odd so that the device is clocked smoothly.  The total
# time for a row is thus 1354 time periods.
#
# There are 1024 rows so the total length of the clock
# table is 1386496 timeperiods.
#
#-FPGA code reserves bits 7 for prst, 8 for SOP, 9 for EOP, 20 for ADC pulse.
#
#
# Mapping of clock lines based on Lab Cable Dwg:
#-CLK1    VrstOff        (Z)
#-CLK2    pC1        (A)
#-CLK3    pC2        (C)
#-CLK4    VnCol        (E)
#-CLK5    VnRow        (G)
#-CLK6    VpRow        (J)
#-CLK7    pRstOn        (L)
#-CLK8    SOP        (reserved)
#-CLK9    EOP        (reserved)
#-CLK10    pRowOn        (T)
#-CLK11    VRowOff        (V)
#-CLK12    VggCl        (X)
#-CLK13    pR2        (N)
#-CLK14    pR1        (R)
#-CLK15    pRefEnable    (d)
#-CLK16    VnpwR        (f)
#-CLK17    VnpwT        (h)
#-CLK18    VnStat        (j)
#-CLK19    unused
#-CLK20    unused
#-CLK21    ADC convert    (reserved)
#-order of labels below determines pinout of clock connector.

TABLELEN        1386496
TIMEPER         1    # ca. 1 microsec per table entry
NBITS           21   # 32 max

VrstOff        L &                                  #set low and stay low
# CLK2:
pC1        H ( 5 5 4 18 ( 4 6 )128 16 26 )1024
# CLK3:
pC2        H ( 5 10 16 6 ( 4 6 )127 4 43 )1024
# CLK4
VnCol        L &
# CLK5
VnRow        L &
# CLK6
VpRow        L &
# CLK7  
prston        L 1329 ( 25 1329 )*
# CLK8
-SOP        L &
# CLK9
-EOP        L &
# CLK10
pRowOn    H &
# CLK11
VRowOff    L &
# CLK12
VggCl        L &
# CLK13:
pR2        H  5 10 1339 ( 1355 1353 )*        # Start asserted for 5

timeper, then off for five, then alternate
# CLK14:
pR1        H  5 5 4 1341 ( 1353 1355 )*        # Start asserted for 5

timeper, then off for five, then alternate
# CLK15
pRefEnable    L &
# CLK16
VnpwR        L &
# CLK17
VnpwT        L &
# CLK18
VnStat        L &
Z19        L &
Z20        L &
# CLK21
-CTC        L ( 30 1 9 1 ( 4 1 )253 21 1 26 )*