Tuesday, May 17, 2011

Noise

Now that the rolling is not, it's time to move on to the pickup/noise issue to see whether it can be isolated/eliminated.

Started by measuring (again) the noise on one of the bias supplies.  Using a cable that Jim had made specifically for this purpose, I connected the front-panel monitor for an unused supply (DC19) to all four amplifier inputs simultaneously.  This seemed worth doing since the noise of the array is very unlikely to be any better than the noise on its DC supply lines, so it can provide an estimate of the system noise floor.

In this configuration I collected a series of four-scan SUTR files at 33 ctdelay.  I then differenced each pair of scans in each of the files to create the equivalent of a CDS.  Then to see how repeatable the 'CDS' results are I differenced the two CDS frames from each of the files to get a single difference frame for each SUTR file.  Since any fixed pattern should be removed by the CDS, this areal standard deviation in the final difference frame should be an estimate of the read noise, but increased by root 2 due to the quadrature sum of the noise in the individual CDS frames.  It's a valid way to calculate noise (Bill and Judy did all their SIRTF array testing at Rochester this way), but it does tend to suppress very low frequencies (below 1Hz in this case). Clear as mud?

Using DC19 as an input source, the noise estimate obtained is about 1.2DN, or ~40 electrons.  Not sure whether/how much 60Hz is contributing to this, but there is a noticeable diagonal (thus not 60Hz) 'pickup' across the scans which is obviously not coming from the array. Here is an example of a 'bias supply' frame:

Difference of two 'CDS' frames taken with DC19
as the input source to the ADCs.


Moving next to the bare mux as an input, with my finger over the pinhole to restrict the light, we see a noise estimate more like 3.3DN, or 115 electrons.  That number seems a bit high, but I'm not going to get too excited about it just yet since there is still some light leaking in and I haven't tried to optimize anything yet.

Interestingly, in every eighth scan pixel 1022,1023 (Row, Col, counting from 0) is about 8kDN away from the median in these files.  No idea why, but this causes the autoscaled blinking in Justin's gui if we don't limit the scaling to the orange box.  In this data I've just replaced that pixel with the array median...otherwise it really screws things up.

To give an idea what the data looks like, I'm including examples of the frames from one of the bare mux fits files:

Single scan of bare mux, pinhole covered, but light still leaking in


A 'CDS' difference made from two single scans
(should mitigate fixed-pattern defects at some level, but photons remain)

A difference between two CDS differences, which should
subtract both fixed pattern and photon flux to first order...obviously not perfect

I can see some banding that looks like ~20-row (60Hz) pickup in the last image above, so there is room for improvement.  It's not so pronounced as I remember it from the IRTF frames....I'll run the same script on those files to compare but I'm out the next three days, so there will be a gap.  There is an IDL script on the mini called exesURnoise.pro if someone else wants to look at other data with it.

All Rock, no Roll

With a single adjustment to the clock table generating file, the rolling was eliminated, thank you Justin.  Not sure why it ever worked without this change, but according to Justin:

The SOP line is not used. The EOP is crucial....The EOP is part of the clocking table and the state-machine ouputing clocks uses it to re-start clocking at the strart of the table. If EOP were not configured then the clocking and converting (coadding)components would get out of sync with the array size.

I added an EOP to the clock table and the rolling stopped :)  The key line added to the .btg (pasted below for reference) is 'and EOP !1 H 1', and it tells the btg app to strobe the EOP bit for one time period at the end of the file.


TABLELEN        1361920
TIMEPER         1    # ca. 1 microsec per table entry
NBITS           21   # 32 max


VrstOff        L &                     #set low and stay low
# CLK2:
pC1            H ( 5 5 4 6 ( 4 6 )128 4 26 )*
# CLK3:
pC2            H ( 5 10 4 6 ( 4 6 )127 4 31 )*
# CLK4
VnCol          L &
# CLK5
VnRow          L &
# CLK6
VpRow          L &
# CLK7   
prston         L 1305 ( 25 2635 )*
# CLK8
-SOP           L &
# CLK9
-EOP           L &
# CLK10
pRowOn         L 1305 ( 25 2635 )*
# CLK11
VRowOff        L &
# CLK12
VggCl          L &
# CLK13:
pR2           H  5 1327 ( 1329 1331 )*
# CLK14:
pR1           H  5 5 1321 ( 1331 1329 )*
# CLK15
pRefEnable    L &
# CLK16
VnpwR         L &
# CLK17
VnpwT         L &
# CLK18
VnStat        L &
Z19           L &
Z20           L &
# CLK21
-CTC          L ( 13 1 4 1 ( 4 1 )253 4 1 41 )*
and EOP !1 H 1


Monday, May 09, 2011

Bare mux in lab dewar

I have a bare mux running in the benchtop dewar.  Here is a nicely detailed picture of the lab ceiling, imaged through a pinhole.



The image is still rolling across the display, and it may be easier to fix now that it seems the have gotten over its 'intermittent' phase.

I have spent way too much time re-acquainting myself with the wiring issues we have in the various PBMA documents.  I have a spreadsheet that accurately captures the present state of the wiring from the eBox to the detector array, but we have a semi-big job ahead of us to get everything consistent between the bench dewar and EXES, and to then properly document the wiring of the system.

Here for perpetual reference are the bias/clock assignments for the bench dewar...they may need to be revised, but the 'Warm' column contains the values used to get the image above:


SB375 Bench Dewar Clock/Bias Assignments
Line
Cold
Warm
DC01:  N/C


DC02:  VddOutRef
-0.1V
-0.1V
DC03:  VddOut4
-2.0V
-2.0V
DC04:  VddOut3
-2.0V
-2.0V
DC05:  VddOut2
-2.0V
-2.0V
DC06:  VddOut1
-2.0V
-2.0V
DC07:  VssUC
0V
0V
DC08:  VslewRef
-2.0V  (-1.44V loaded)
-2.0V  (-1.64V loaded)
DC09:  VnStat
-6.5V
-5.3V
DC10:  VddCl
-2.0V
-2.0V
DC11:  VddUC/VRST
-2.25V
-3.6V
DC12:  VDET
-3.25V
-3.25V



CLK01:  VrstOff
-0.5V/-0.5V
-0.0V/-0.0V
CLK02:  ØC1
-0.8V/-3.9V
-0.7V/-3.1V
CLK03:  ØC2
-0.8V/-3.9V
-0.7V/-3.1V
CLK04:  VnCol
-4.5V/-4.5V
-3.1V/-3.1V
CLK05:  VnRow
-4.5V/-4.5V
-3.0V/-3.0V
CLK06:  VpRow/Col
-0.8V/-0.8V
-0.7V/-0.7V
CLK07:  ØRstOn
-2.0V/-5.0V
-0.8V/-4.0V
CLK10:  ØRowOn
-3.9V/-3.9V
-3.2V/-3.2V
CLK11:  VRowOff
 -1.1V/-1.1V
0.1V/0.1V
CLK12:  VggCl
0V/0V
-1.0V/-1.0V
CLK13:  ØR2
-0.8V/-3.9V
-0.8V/-3.1V
CLK14:  ØR1
-0.8V/-3.9V
-0.8V/-3.1V
CLK15:  ØRefEn
-0.1V
-0.1V
CLK16: VnPwR
-6.5V
-5.3V