The image is still rolling across the display, and it may be easier to fix now that it seems the have gotten over its 'intermittent' phase.
I have spent way too much time re-acquainting myself with the wiring issues we have in the various PBMA documents. I have a spreadsheet that accurately captures the present state of the wiring from the eBox to the detector array, but we have a semi-big job ahead of us to get everything consistent between the bench dewar and EXES, and to then properly document the wiring of the system.
Here for perpetual reference are the bias/clock assignments for the bench dewar...they may need to be revised, but the 'Warm' column contains the values used to get the image above:
SB375 Bench Dewar Clock/Bias Assignments
|
Line
|
Cold
|
Warm
|
|
DC01: N/C
|
|
|
|
DC02: VddOutRef
|
-0.1V
|
-0.1V
|
|
DC03: VddOut4
|
-2.0V
|
-2.0V
|
|
DC04: VddOut3
|
-2.0V
|
-2.0V
|
|
DC05: VddOut2
|
-2.0V
|
-2.0V
|
|
DC06: VddOut1
|
-2.0V
|
-2.0V
|
|
DC07: VssUC
|
0V
|
0V
|
|
DC08: VslewRef
|
-2.0V (-1.44V loaded)
|
-2.0V (-1.64V loaded)
|
|
DC09: VnStat
|
-6.5V
|
-5.3V
|
|
DC10: VddCl
|
-2.0V
|
-2.0V
|
|
DC11: VddUC/VRST
|
-2.25V
|
-3.6V
|
|
DC12: VDET
|
-3.25V
|
-3.25V
|
|
|
|
|
|
CLK01: VrstOff
|
-0.5V/-0.5V
|
-0.0V/-0.0V
|
|
CLK02: ØC1
|
-0.8V/-3.9V
|
-0.7V/-3.1V
|
|
CLK03: ØC2
|
-0.8V/-3.9V
|
-0.7V/-3.1V
|
|
CLK04: VnCol
|
-4.5V/-4.5V
|
-3.1V/-3.1V
|
|
CLK05: VnRow
|
-4.5V/-4.5V
|
-3.0V/-3.0V
|
|
CLK06: VpRow/Col
|
-0.8V/-0.8V
|
-0.7V/-0.7V
|
|
CLK07: ØRstOn
|
-2.0V/-5.0V
|
-0.8V/-4.0V
|
|
CLK10: ØRowOn
|
-3.9V/-3.9V
|
-3.2V/-3.2V
|
|
CLK11: VRowOff
|
-1.1V/-1.1V
|
0.1V/0.1V
|
|
CLK12: VggCl
|
0V/0V
|
-1.0V/-1.0V
|
|
CLK13: ØR2
|
-0.8V/-3.9V
|
-0.8V/-3.1V
|
|
CLK14: ØR1
|
-0.8V/-3.9V
|
-0.8V/-3.1V
|
|
CLK15: ØRefEn
|
-0.1V
|
-0.1V
|
|
CLK16: VnPwR
|
-6.5V
|
-5.3V
|
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