| Ebox DC & Clock Voltages | |||||
| as of 15-Feb-2018 | |||||
| DC | Purpose | Voltage | |||
| 01 | unused | -9.95 | |||
| 02 | Vdd OutRef | -2.252 | |||
| 03 | Vdd Out4 | -2.196 | (-2.197) | ||
| 04 | Vdd Out3 | -2.192 | |||
| 05 | Vdd Out2 | -2.186 | (-2.187) | ||
| 06 | Vdd Out1 | -2.174 | |||
| 07 | Vgg UC | -0.04 | |||
| 08 | VSlew Ref | -1.502 | |||
| 09 | Vn Stat | -6.039 | (-6.041) | ||
| 10 | Vdd Cl | -2.013 | |||
| 11 | Vdd UC | -2.486 | |||
| 12 | Vdet | -3.504 | ~(-4.500) | for 2 V bias | |
| Clock | Purpose | Voltage | |||
| 01 | VrstOff | -1.792 | |||
| 02 | ϕC1 | -1.779 | (-1.780) | ||
| 03 | ϕC2 | -1.746 | |||
| 04 | Vn Col | -3.988 | |||
| 05 | Vn Row | -4.045 | (-4.046) | ||
| 06 | Vp Row/Col | -0.772 | |||
| 07 | ϕRstOn | -2.089 | |||
| 10 | ϕRstOff | -3.185 | |||
| 11 | VRowOff | -1.796 | |||
| 12 | Vgg CL | -0.062 | |||
| 13 | ϕR2 | -1.993 | |||
| 14 | ϕR1 | -2.014 | (-2.015) | ||
| 15 | ϕRefEnable | -3.176 |
Thursday, February 15, 2018
CD36 Voltages at Start
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1 comment:
Some of the clocks have to be measured with an oscilloscope.
Here's what I measured during the week of Apr 2-6, 2018.
(the -6.0 are unassigned I guess).
All the even/odd action was changing the upper rail on CLK 10.
Clock Purpose Voltage
01 VrstOff -1.8
02 ϕC1 -0.8/-3.2
03 ϕC2 -0.8/-3.2
04 Vn Col -4.0
05 Vn Row -4.0
06 Vp Row/Col -0.8
07 ϕRstOn -2.0
08 -6.0
09 -6.0
10 ϕRstOff -2.0/-3.2 ---> changed to -1.5/-3.2 V on 2018 Apr 5.
11 VRowOff -1.8
12 Vgg CL 0.0
13 ϕR2 -0.8/-3.2
14 ϕR1 -0.8/-3.2
15 ϕRefEnable -3.2
16 -6.0
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